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FEDL9213-01
1 Semiconductor ML9213
GENERAL DESCRIPTION
This version: Oct. 2001
56-Bit Duplex/Triplex (1/2 duty/1/3 duty) VFD Controller/Driver with Anode Digital Dimming
The ML9213 is a full CMOS controller/driver for Duplex or Triplex (1/2 duty or 1/3 duty) vacuum fluorescent display tube. It consists of a 56-segment driver multiplexed to drive up to 168 segments, and 10-bit digital dimming circuit. ML9213 features a selection of a master mode and a slave mode, and therefore it can be used to expand segments for the VFD driver with keyscan and A/D converter function. ML9213 provides an interface with a microcontroller only by three signal lines: DATA IN, CLOCK and CS.
FEATURES
N Logic supply voltage (VDD) : 5.0 V H10% N Driver supply voltage (VDISP) : 8.0 to 18.0 V N Duplex/Triplex (1/2 duty / 1/3 duty) selectable DUP/TRI = 1/2 duty selectable at "H" level DUP/TRI = 1/3 duty selectable at "L" level N Number of display segments 112 segments max. (during 1/2 duty mode) 168 segments max. (during 1/3 duty mode) N Master/Slave selectable : Master mode M/S = "H" level M/S = "L" level : Slave mode N Interface with a microcontroller Three lines: CS, CLOCK, and DATA IN N 56-segment driver outputs : IOH = -5.0 mA at VOH = VDISP-0.8 V (SEG1 to 37) (can be directly connected to VFD tube : IOH = -10.0 mA at VOH = VDISP-0.8 V (SEG38 to 56) and requires no external resistors) : IOL = 500 2A at VOL = 2.0 V (SEG1 to 56) N 3-grid pre-driver outputs : IOH = -5.0 mA at VOH = VDISP-0.8 V (requires external drivers) IOL = 10.0 mA at VOL = 2.0 V N Logic outputs : IOH = -200 2A at VOH = VDD-0.8 V IOL = 200 2A at VOL = 0.8 V N Built-in anode digital dimming circuit (10-bit resolution) N Built-in oscillation circuit (external resistor and capacitor) N Built-in Power-On-Reset circuit N Package options: 80-pin plastic QFP (QFP80-P-1420-0.80-BK) Product name: ML9213GA 80-pin plastic QFP (QFP80-P-1414-0.65-K) Product name: ML9213GP
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FEDL9213-01
1 Semiconductor
ML9213
BLOCK DIAGRAM
SEG1
SEG56
GRID1 GRID2GRID3
VDISP D-GND VDD L-GND Power On Reset 0H 4H
56 Segment Driver
3 Grid Pre Driver
POR Out1-56 168 to 56 Segment Control In1-56 In1-56
In1-56
POR
Mode Select In1-3
1H 0H
POR
Out1-56 Segment Latch1 In1-56
2H 0H
POR
Out1-56 Segment Latch2 In1-56
3H 0H
POR
Out1-56 Segment Latch3 In1-56
CS CLOCK DATA IN Control
Out1-3 3 bit Shift Register POR
Out1-56 32 bit Shift Register POR
4H
POR
In1-10 Dimming Latch Out1-10
OSC0
OSC POR
10 bit Digital Dimming
DIM IN SYNC IN1 SYNC IN2 M/S DUP/TRI Timing Generator
DIM OUT SYNC OUT1 SYNC OUT2
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FEDL9213-01
1 Semiconductor
ML9213
PIN CONFIGURATION (TOP VIEW)
80 VDISP 79 SEG37 78 SEG36 77 SEG35 76 SEG34 75 SEG33 74 SEG32 73 SEG31 72 SEG30 71 SEG29 70 SEG28 69 SEG27 68 SEG26 67 SEG25 66 SEG24 65 VDISP SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 GRID1 GRID2 GRID3 NC D-GND 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VDD 25 DIM IN 26 SYNC IN1 27 SYNC IN2 28 CS 29 CLOCK 30 DATA IN 31 NC 32 L-GND 33 OSC0 34 DUP/TRI 35 M/S 36 SYNC OUT2 37 SYNC OUT1 38 DIM OUT 39 D-GND 40
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 NC
NC: No connection
ML9213GA 80-Pin Plastic QFP (QFP80-P-1420-0.80-BK)
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FEDL9213-01
1 Semiconductor
ML9213
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
SEG39 SEG38 VDISP SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 VDISP SEG23 SEG22
SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 GRID1 GRID2 GRID3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2
NC D-GND VDD DIM IN SYNC IN1 SYNC IN2 CS CLOCK DATA IN NC L-GND OSC0 DUP/TRI M/S SYNC OUT2 SYNC OUT1 DIM OUT D-GND NC SEG1 NC: No connection
ML9213GP 80-Pin Plastic QFP (QFP80-P-1414-0.65-K)
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1 Semiconductor
ML9213
PIN DESCRIPTIONS
Symbol VDISP VDD D-GND L-GND SEG1 to 37 Pin ML9213GA ML9213GP 65, 80 25 24, 40 33 42 to 64, 66 to 79 63, 78 23 22, 38 31 40 to 62, 64 to 77 Type -- -- -- -- O Description Power supply pins for VFD driver circuit. These should be connected externally. Power supply pin for logic drive. D-GND is ground pin for the VFD driver circuit. L-GND is ground pin for the logic circuit. These should be connected externally. Segment (anode) signal output pins for a VFD tube. These pins can be directly connected to the VFD tube. External circuit is not required. IOH d -5 mA Segment (anode) signal output pins for a VFD tube. These pins can be directly connected to the VFD tube. External circuit is not required. IOH d -10 mA Inverted Grid signal output pins. Since these pins are connected to the pre-driver, an external circuit is required. IOL d 10 mA Chip select input pin. Data is not transferred when CS is set to a Low level. Shift clock input pin. Serial data shifts at the rising edge of the CLOCK. Serial data input pin (positive logic). Data is input to the shift register at the rising edge of the CLOCK signal. Duplex/Triplex operation select input pin. Duplex (1/2 duty) operation is selected when this pin is set to VDD. Triplex (1/3 duty) operation is selected when this pin is set to LGND. Master/Slave mode select input pin. Master mode is selected when this pin is set to VDD. Slave mode is selected when this pin is set to L-GND. Dimming pulse input. When the slave mode is selected, connect this pin to the master side DIM OUT pin. The pulse width of all the segment outputs is controlled by an input pulse width of DIM IN. When the master mode is selected, input to this pin is ignored; therefore, connect this pin to VDD or L-GND. The pulse width of all the segment outputs is controlled by the built-in digital dimming circuit, and the pulse width of all the grid outputs is controlled by the internal timing generator. Synchronous signal input. When the slave mode is selected, connect these pins to the master side SYN COUT1 and 2 pins. When the master mode is selected, input to these pins is ignored; therefore, connect these pins to VDD or L-GND. Dimming pulse output. Connect this pin to the slave side DIM IN pin.
SEG38 to 56 GRID1 GRID2 GRID3 CS CLOCK DATA IN
1 to 19 20 21 22 29 30 31
79, 80, 1 to 17 18 19 20 27 28 29
O
O
I I I
DUP/TRI
35
33
I
M/S
36
34
I
DIM IN
26
24
I
SYNC IN1
27
25 I
SYNC IN2 DIM OUT
28 39
26 37 O
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FEDL9213-01
1 Semiconductor
ML9213
Symbol SYNC OUT1 SYNC OUT2
Pin ML9213GA ML9213GP 38 37 36 35
Type O
Description Synchronous signal output. Connect these pins to the slave side SYNC IN1 and 2 pins. RC oscillator connecting pins. Oscillation frequency depends on display tubes to be used. For details, refer to ELECTRICAL CHARACTERISTICS. VDD OSC0
OSC0
34
32
I/O
R C
ABSOLUTE MAXIMUM RATINGS
Parameter Driver Supply Voltage Logic Supply Voltage Input Voltage Power Dissipation Storage Temperature Symbol VDISP VDD VIN PD TSTG IO1 Output Current IO2 IO3 IO4 Tat25C Condition -- -- -- QFP80-P-1420-0.80-BK QFP80-P-1414-0.65-K -- SEG1 to 37 SEG38 to 56 GRID1 to 3 DIM OUT, SYNC OUT1, SYNC OUT2 Rating -0.3 to +20 -0.3 to +6.5 -0.3 to VDD+0.3 342 343 -55 to +150 -10.0 to +2.0 -20.0 to +2.0 -10.0 to +20.0 -2.0 to +2.0 Unit V V V mW C mA mA mA mA
RECOMMENDED OPERATING CONDITIONS
Parameter Driver Supply Voltage Logic Supply Voltage High Level Input Voltage Low Level Input Voltage Clock Frequency Oscillation Frequency Frame Frequency Operating Temperature Symbol VDISP VDD VIH VIL fC fOSC fFR TOP Condition -- -- All inputs except OSC0 All inputs except OSC0 -- R = 10 k: r 5%, C = 27 pF r 5% R = 10 k: r 5%, C = 27 pF r 5% -- 1/3 Duty 1/2 Duty Min. 8.0 4.5 0.8VDD -- -- 2.2 179 268 -40 Typ. 13.0 5.0 -- -- -- 3.3 269 403 -- Max. 18.0 5.5 -- 0.2VDD 2.0 4.4 358 538 +105 Unit V V V V MHz MHz Hz Hz C
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FEDL9213-01
1 Semiconductor
ML9213
ELECTRICAL CHARACTERISTICS
DC Characteristics
Ta = -40 to +105C, VDISP = 8.0 to 18.0 V, VDD = 4.5 to 5.5 V Parameter High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Symbol VIH VIL IIH IIL VOH1 High Level Output Voltage VOH2 VOH3 VOH4 VOL1 Low Level Output Voltage VOL2 VOL3 VOL4 Supply Current IDISP IDD Applied pin *1) *1) *1) *1) SEG1-37 SEG38-56 GRID1-3 *2) SEG1-37 SEG38-56 GRID1-3 *2) VDISP VDD VDD = 4.5 V VDD = 4.5V Condition -- -- VIH = VDD VIL = GND IOH1 = -5 mA VDISP = 9.5 V IOH2 = -10 mA IOH3 = -5 mA IOH4 = -200 PA IOL1 = 500 PA VDISP = 9.5 V IOL2 = 500 PA IOL3 = 10 mA IOL4 = 200 PA R=10 k: 5%,C=27 pF 5%, no load Min. 0.8VDD -- -1.0 -1.0 VDISP-0.8 VDISP-0.8 VDISP-0.8 VDD-0.8 -- -- -- -- -- -- Max. -- 0.2VDD +1.0 +1.0 -- -- -- -- 2.0 2.0 2.0 0.8 100 5.0 Unit V V PA PA V V V V V V V V PA mA
*1) CS, CLOCK, DATA IN, DIM IN, SYNC IN1, SYNC IN2, M/S, DUP/TRI *2) DIM OUT, SYNC OUT1, SYNC OUT2
AC Characteristics
Ta = -40 to +105C, VDISP = 8.0 to 18.0 V, VDD = 4.5 to 5.5 V Parameter Clock Frequency Clock Pulse Width Data Setup Time Data Hold Time CS Off Time CS Setup Time (CS-Clock) CS Hold Time (Clock-CS) CS Wait Time Output Slew Rate Time VDD Rise Time VDD Off Time Symbol fC tCW tDS tDH tCSL tCSS tCSH tRSOFF tR tF tPRZ tPOF CL = 100 pF Condition -- -- -- -- -- -- -- -- tR = 20% to 80% tF = 80% to 20% Min. -- 200 200 200 20 200 200 400 -- -- -- 5.0 Max. 2.0 -- -- -- -- -- -- -- 2.0 2.0 100 -- Unit MHz ns ns ns Ps ns ns Ps Ps Ps Ps ms
Mounted in a unit Mounted in a unit, VDD = 0.0 V
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FEDL9213-01
1 Semiconductor
ML9213
TIIMING DIAGRAM
N Data Input Timing
tCSL CS tCSS tCW CLOCK tDS DATA IN VALID VALID tDH VALID VALID 1/fC tCW tCSH -0.8VDD -0.2VDD -0.8VDD -0.2VDD -0.8VDD -0.2VDD
N Reset Timing
VDD
tPRZ tRSOFF
tPOF
-0.8VDD -0.0 V -0.8VDD -0.0 V
CS
N Driver Output Timing
SEG1-56, GRID1-3 tR tF tR -0.8VDISP -0.2VDISP
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1 Semiconductor
ML9213
N Output Timing (Duplex Operation) *1 bit time = 4/fOSC Solid line: Indicates that the anode dimming data is 1016/1024 in the master mode. Chain line: Indicates that the anode dimming data is 64/1024 in the master mode.
N Output Timing (Triplex Operation) *1 bit time = 4/fOSC Solid line: Indicates that the anode dimming data is 1016/1024 in the master mode. Chain line: Indicates that the anode dimming data is 64/1024 in the master mode.
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FEDL9213-01
1 Semiconductor
ML9213
FUNCTIONAL DESCRIPTION
Power-on Reset When power is turned on, the ML9213 is initialized by the internal power-on reset circuit. The status of the internal circuit after initialization is as follows: N The contents of the shift registers and latches are set to "0". N The anode dimming duty cycle is set to "0". N All segment outputs (SEG1 to 56) are set to Low level. N The GRID1 output is set to Low level. N The GRID2 and GRID3 outputs are set to High level. Data Transfer Method Data can be transferred between the rising edge and the next falling edge of chip select input. The mode data, segment data and anode dimming data are written by a serial transfer method. The serial data is input to the shift register at the rising edge of a shift clock pulse. The mode data (M0 to M2) must be transferred after the segment data and anode dimming data succeedingly. When the chip select input falls, an internal LOAD signal is automatically generated and data is loaded to the latches. Set the shift clock to a High level except during data transfer.
CS CLOCK DATA IN
Segment data or dimming data M0 M1 M2
Mode data
Function Mode Function mode is selected by the mode data (M0 to M2). The relation between function mode and mode data is as follows:
FUNCTION MODE 0 1 2 3 4 OPERATING MODE Segment Data for GRID1-3 Input Segment Data for GRID1 Input Segment Data for GRID2 Input Segment Data for GRID3 Input Digital Dimming Data Input MODE DATA M0 0 1 0 1 0 M1 0 0 1 1 0 M2 0 0 0 0 1
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FEDL9213-01
1 Semiconductor
ML9213
Segment Data Input [Function Mode: 0 to 3] N ML9213 receives the segment data when function mode 0 to 3 are selected. N The same segment data is transferred to the 3 segment data latches corresponding to GRID1 to 3 at the same time when the function mode 0 is selected. N The segment data is transferred to only one segment data latch corresponding to the specified GRID when the function mode is 1, 2 or 3 is selected. N Segment output (SEG1 to 56) becomes High level (lighting) when the segment data (S1 to S56) is set to "1". [Data Format] Input Data : 59 bits Segment Data: 56 bits Mode Data : 3 bits
Bit Input Data 1 S1 2 S2 3 S3 4 S4 .......... .......... 53 S53 54 S54 55 S55 56 S56 57 M0 58 M1 Mode Data (3 bits) 59 M2
Segment Data (56 bits)
[Bit correspondence between segment output and segment data]
Segment output Segment data Segment output Segment data Segment output Segment data Segment output Segment data
1 S1 17 S17 33 S33 49 S49
2 S2 18 S18 34 S34 50 S50
3 S3 19 S19 35 S35 51 S51
4 S4 20 S20 36 S36 52 S52
5 S5 21 S21 37 S37 53 S53
6 S6 22 S22 38 S38 54 S54
7 S7 23 S23 39 S39 55 S55
8 S8 24 S24 40 S40 56 S56
9 S9 25 S25 41 S41 -----
10 S10 26 S26 42 S42 -----
11 S11 27 S27 43 S43 -----
12 S12 28 S28 44 S44 -----
13 S13 29 S29 45 S45 -----
14 S14 30 S30 46 S46 -----
15 S15 31 S31 47 S47 -----
16 S16 32 S32 48 S48 -----
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FEDL9213-01
1 Semiconductor
ML9213
Anode Dimming Data Input [Function Mode: 4] N ML9213 receives the anode dimming data when function mode 4 is selected. N The output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid. N The 10-bit anode dimming data is input from LSB. [Data Format] Input Data : 13 bits Anode Dimming Data : 10 bits Mode Data : 3 bits
Bit Input Data 1 D1 LSB Digital Dimming Data (10bits) 2 D2 3 D3 4 D4 5 D5 6 D6 7 D7 8 D8 9 D9 10 D10 MSB Mode Data (3bits) (MSB) D7 0 0 1 1 1 1 D8 0 0 1 1 1 1 D9 0 0 1 1 1 1 D10 0 0 1 1 1 1 11 M0 12 M1 13 M2
(LSB) D1 0 1 1 0 1 1 D2 0 0 1 0 0 1 D3 0 0 1 0 0 1 D4 0 0 0 1 1 1
Dimming Data D5 0 0 1 1 1 1 D6 0 0 1 1 1 1
Duty Cycle 0/1024 1/1024 1015/1024 1016/1024 1016/1024 1016/1024
Master Mode Master Mode is selected when M/S pin is set at High level. The master mode operation is as follows: N Input to DIM IN, SYNC IN1 and SYNC IN2 is ignored, and these pins should be connected to L-GND or VDD. N The pulse width of SEG1 to SEG56 is controlled by the internal digital dimming circuit. N The segment data corresponding to GRID1 to 3 is selected by the internal timing generator.
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1 Semiconductor
ML9213
Slave Mode Slave Mode is selected when M/S pin is set at Low level. The slave mode operation is as follows: N Output from internal anode dimming circuit is ignored. Connect the DIM IN, SYNC IN1 and SYNC IN2 pins to the master side DIM OUT, SYNC OUT1 and SYNC OUT2 pins respectively. N The pulse width of SEG1 to 56 is controlled by the pulse width of DIM IN signal. N The segment data corresponding to GRID1 to 3 is selected by combinations of the SYNC IN1 and SYNC IN2 signals. N The output levels of GRID1 to 3 are set at High level. The output levels of DIM OUT, SYNC OUT1 and SYNC OUT2 are set at Low level.
[Correspondence between SYNC IN1, 2 and GRID1 to 3] SYNC IN 1 0 1 0 1 SYNC IN 2 0 0 1 1 Segment Latch No Latch1 Latch2 Latch3 GRID No GRID1 GRID2 GRID3 [Correspondence between DIM IN and SEG1 to 56] DIM IN 0 1 SEG1 to 56 Low High
Note: Low: Lights OFF High: Lights ON
13/19
1. Circuit for the duplex VFD tube (2-Grid K 112-Anode) K K K
APPLICATION CIRCUITS
1 Semiconductor
VDD VDD
VDISP SEG1 VDD
VDD
VDISP SEG1 SEG56 GRID1 GRID2 GRID3
S1 S2 S3 G1 G2 S110 S111 S112
VDISP
VDD
ML9213 (MASTER) SEG56
DUP/TRI M/S SYNC IN2 GRID1 GRID2 GRID3 SYNC IN1 DIM IN CS DATA IN CLOCK
ML9213 (SLAVE)
DUP/TRI
M/S
GND SYNC IN2 SYNC IN1 DIM IN CS DATA IN CLOCK
GND
SYNC OUT2 SYNC OUT1 DIM OUT
SYNC OUT2 SYNC OUT1 DIM OUT
Duplex VFD Tube
Microcontroller GND
VDD
R
VDD
R
Ef
OSC0 C GND L-GND D-GND C GND
OSC0 L-GND D-GND
FEDL9213-01
ML9213
14/19
2. Circuit for the triplex VFD tube (3-Grid K 112-Anode) K K K
1 Semiconductor
VDD
VDISP SEG1 SEG56
VDD
VDISP SEG1 SEG56
VDD
ML9213 (MASTER) M/S
DUP/TRI SYNC IN2 SYNC IN1 DIM IN CS DATA IN CLOCK
ML9213 (SLAVE) M/S
DUP/TRI GND SYNC IN2 SYNC IN1 DIM IN CS DATA IN CLOCK
VDISP
VDD
GRID1 GRID2 GRID3 SYNC OUT2 SYNC OUT1 DIM OUT
GRID1 GRID2 GRID3 SYNC OUT2 SYNC OUT1 DIM OUT
S1 S2 S3 G1 G2 G3 S110 S111 S112
Microcontroller GND
GND
Triplex VFD Tube Ef
VDD
R C GND
VDD
R
OSC0 L-GND
OSC0 D-GND C GND L-GND D-GND
FEDL9213-01
ML9213
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FEDL9213-01
1 Semiconductor
ML9213
NOTES ON TURNING POWER ON/OFF
N Connect L-GND and D-GND externally to be an equal potential voltage. N To avoid wrong operations, turn on the driver power supply after turning on the logic power supply. Conversely, turn off the logic power supply after turning off the driver power supply.
[Voltage] VDISP VDD [Time]
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FEDL9213-01
1 Semiconductor
ML9213
PACKAGE DIMENSIONS
(Unit: mm)
QFP80-P-1420-0.80-BK
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 1.27 TYP. 4/Nov. 28, 1996
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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FEDL9213-01
1 Semiconductor
ML9213
(Unit: mm)
QFP80-P-1414-0.65-K
Mirror finish
5
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 0.85 TYP. 3/Nov. 28, 1996
Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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1 Semiconductor
ML9213
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2001 Oki Electric Industry Co., Ltd.
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